The present invention relates to a semiconductor device which incorporates a memory cell array, such as a static RAM (random access memory), or the like.
The trend of the semiconductor device industry has been such that, in a semiconductor device wherein a system is implemented on a chip, i.e., a so-called system LSI (large-scale integrated circuit), a large capacity semiconductor memory is incorporated in some cases, and a large number of small-capacity semiconductor memories are incorporated in other cases. In view of the chip layout efficiency, it has been demanded to use an area over a memory block as a wire region for signals transferred between logic circuits incorporated together with the memory block and signals transferred between an IO (input/output) pad and the logic circuits. However, a typical layout of such a semiconductor memory is such that word lines used for selection of a memory cell to be accessed and bit lines used for data transmission between memory cells and external devices are arranged to extend over a memory cell array. Therefore, there is a possibility that crosstalk occurs between these lines and signal lines running between the logic circuits over the memory, and the crosstalk causes characteristic deteriorations and malfunctions on the memory side. Especially, in a type of a semiconductor memory wherein a very small potential variation is amplified, the wire layout needs to be such that no coupling capacitance is generated between the bit lines and the signal lines of an overlying layer.
A technique which addresses the above points has been known wherein signal lines of an upper layer are arranged to cross word lines at right angles such that coupling capacitance is unlikely to be generated, and meanwhile, complementary bit line pairs running alongside the signal lines are arranged with equal intervals such that coupling capacitance is uniformly generated between the signal lines and the complementary bit line pairs (see Japanese Laid-Open Patent Publication No. 1-272149). Further, another technique has been known wherein signal lines are provided in a word line backing portion adjacent to a memory cell array (see Japanese Laid-Open Patent Publication No. 2001-257266).
However, Japanese Laid-Open Patent Publication No. 1-272149 does not mention the layout control of signal lines. Especially, a control process for arranging wires with equal intervals with respect to complementary bit line pairs based on an automatic wiring scheme has been generally impossible.
In the technique disclosed in Japanese Laid-Open Patent Publication No. 2001-257266, a memory cell array region, which occupies a considerably large part of a memory block, is covered with a metal pattern, and a wire channel which can pass over the memory block is limited. Therefore, the wiring efficiency is low.
Furthermore, in both of the above techniques, the running direction of signal lines, which run across an upper layer, with respect to the arrangement direction of the memory block is limited, and a rotation arrangement of memory blocks needs to be carried out according to the direction of metal wires which is determined in an automatic wiring process over a semiconductor device. Therefore, there is a high possibility that such decreased arrangement flexibility generates a dead space and causes an area loss. In the case where the layout is designed with a priority given to arrangement of the memory blocks, it is necessary to change metal wire layers at a position immediately before a memory block is traversed. Therefore, an area loss is caused even in this case, and such wiring control requires troublesome efforts, resulting in inefficient production.